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1 digital dc/dc controller with drivers and auto compensation ZL6105 the ZL6105 is a digital power controller with integrated mosfet drivers. auto compensation eliminates the need for manual compensation design work. adaptive performance optimization algorithms improve power conversion efficiency. zilker labs digital-dc? technology enables a blend of power conversion performance and power management features. the ZL6105 is designed to be a flexible building block for dc power and can be easily adapted to designs ranging from a single-phase power supply op erating from a 3.3v to a multiphase current sharing supply operating from a 12v input. the ZL6105 eliminates the need for complicated power supply managers as well as numerous external discrete components. the ZL6105 uses the i 2 c/smbus? with pmbus? protocol for communication with a host cont roller and the digital-dc bus for communication between zilker labs devices. the ZL6105 is pin for pin comp atible with the zl2008. the pola v out table and compensation table have been removed. a new single resistor v out table and the auto compensation feature have been added. related literature* (see page 34) ?see an2032 , ?nlr configuration for ddc products? ?see an2033 , ?zilker labs pmbus command set - ddc products? ?see an2034 , ?configuring current sharing on the zl2004 and zl2006? ?see an2035 , ?compensation using compzl?? features power conversion ? efficient synchronous buck controller ? auto compensating pid filter ? adaptive light load efficiency optimization ? 3v to 14v input range ? 0.54v to 5.5v output range (with margin) ? 1% output voltage accuracy ? internal 3a mosfet drivers ? fast load transient response ? current sharing an d phase interleaving ? snapshot? parameter capture ?pb-free (rohs compliant) power management ? digital soft-start/stop ? power-good/enable ?voltage tracking, sequ encing and margining ? voltage, current and temperature monitoring ?i 2 c/smbus interface, pmbus compatible ? output voltage and current protection ? internal non-volatile memory (nvm) applications ? servers/storage equipment ? telecom/datacom equipment ? power supply modules current sense ldo temp sensor v ss vtrk mgn vr vdd bst gh sw isena isenb power driver xtemp pwm gl i 2 c scl sda salrt sa management en pg cfg uvlo ph_en ilim fc monitor controller v25 sync vsen+ pgnd sgnd dgnd adc non- volatile memory ddc vsen- figure 1. block diagram load current (a) efficiency (%) 65 70 80 75 85 95 90 100 2 14 0 6 4 812 10 60 55 50 16 18 20 v in = 12v f sw = 400khz circuit of figure 4 v out = 3.3v v out = 1.5v figure 2. efficiency vs load current 3 february 8, 2011 fn6906.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ZL6105 2 fn6906.3 february 8, 2011 typical application circuit the following application circuit represents a typical implementati on of the ZL6105. for enable using the pmbus, it is recommen ded to tie the enable pin (en) to sgnd. ZL6105 1 35 34 33 32 31 30 29 28 10 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 36 dgnd sync sa0 sa1 ilim cfg0 scl sda salrt fc0 fc1 v0 v1 uvlo ss vrtk vsen+ vdd bst gh sw pgnd gl vr isena isenb pg cfg2 en cfg1 mgn ddc xtemp v25 v in 10 f 4 v c in 3 x 10 f 25 v l out i 2 c/smbus 2 power good output c v25 db bat54 cb 1 f 16 v qh ql 2.2 h c out 2 x 47 f 6.3 v 4.7 f c vr 6.3 v v out rtn sgnd epad 12v v25 470 f 2.5 v pos-cap 2*220 f 6.3 v 100 m vsen- enable f.b. 1 ground unification 4.7 f 25 v ddc bus 3 notes: 1. ferrite bead is optional for input noise suppression 2. the i 2 c/smbus requires pull-up resistors. please refer to the i 2 c/smbus specifications for more details. 3. the ddc bus requires a pull-up resistor. the resistance will vary based on the capacitive loading of the bus (and on the nu mber of devices connected). the 10 k default value, assuming a maximum of 100 pf per device, provides the necessary 1 s pull-up rise time. please refer to the ddc bus section for more details. ph_en phase enable figure 3. 12v to 1.8v/16a application circuit ?
ZL6105 3 fn6906.3 february 8, 2011 digital compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sync pll power management temp sensor mux xtemp cfg(0,1,2) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim vdd mosfet drivers sync gen vtrk isenb vdd scl sda salrt > adc adc adc communication dac refcn fc(0,1) ddc voltage sensor vsen- nvm digital compensator i 2 c nlr input voltage bus v out bst sw d-pwm + - vsen+ sync pll power management temp sensor mux xtemp cfg(0,1,2) mgn en v(0,1) pg sa(0,1) ss vr sw vsen isena ilim vdd mosfet drivers sync gen vtrk isenb vdd scl sda salrt > adc adc adc communication dac refcn fc(0,1) ddc voltage sensor vsen- nvm figure 4. ZL6105 block diagram
ZL6105 4 fn6906.3 february 8, 2011 pin configuration ZL6105 (36 ld qfn) top view 27 26 25 24 23 22 21 36 35 34 33 32 10 11 12 13 14 1 2 3 4 5 6 7 dgnd sync sa0 sa1 ilim cfg0 scl vdd bst gh sw pgnd gl vr pg cfg2 ph_en en cfg1 fc0 fc1 v0 v1 uvlo 8 9 20 19 15 31 16 30 isena isenb ss vtrk sda salrt mgn ddc 17 18 vsen+ vsen- 29 28 xtemp v25 exposed paddle* *connect to sgnd pin descriptions pin label type (note 1) description 1 dgnd pwr digital ground. common return for digital signals. connect to low impedance ground plane. 2 sync i/o,m (note 2) clock synchronization input. used to set switching frequency of internal clock or for synchronization to external frequency reference. 3 sa0 i, m serial address select pins. used to assign un ique smbus address to each ic or to enable certain management features. 4sa1 5 ilim i, m current limit select. sets the over current threshold voltag e for isena and isenb. 6 cfg0 i, m configuration pin. used to setup current sharing and non-linear response. 7 scl i/o serial clock. connect to external host and/or to other zl devices. 8 sda i/o serial data. connect to external host and/or to other zl devices. 9 salrt o serial alert. connect to external host if desired. 10 fc0 i loop compensation configuration pins. 11 fc1 12 v0 i output voltage selection pins. used to set v out set-point and v out max. 13 v1 14 uvlo i, m undervoltage lockout selection. sets the minimum value for v dd voltage to enable v out . 15 ss i, m soft start pin. sets the output voltage ramp time during turn-on and turn-off. sets the delay from when en is asserted until the output voltage starts to ramp. 16 vtrk i tracking sense input. used to track an external voltage source. 17 vsen+ i output voltage feedback. connect to output regulation point. 18 vsen- i output voltage feedback. connect to load return or ground regulation point. 19 isenb i differential voltage input for current limit.
ZL6105 5 fn6906.3 february 8, 2011 20 isena i differential voltage input for current limit. high voltage tolerant. 21 vr pwr internal 5v reference used to power internal drivers. 22 gl o low side fet gate drive. 23 pgnd pwr power ground. connect to low impedance ground plane. 24 sw pwr drive train switch node. 25 gh o high-side fet gate drive. 26 bst pwr high-side drive boost voltage. 27 vdd (note 3) pwr supply voltage. 28 v25 pwr internal 2.5v reference used to power internal circuitry. 29 xtemp i external temperature sensor input. connec t to external 2n3904 diode connected transistor. 30 ddc i/o digital-dc bus. (open drain) interoperability between zilker labs devices. 31 mgn i signal that enables margining of output voltage. 32 cfg1 i, m configuration pin. used to se tup clock synchronization and sequencing. 33 en i enable input (active high). pull-up to enable pwm switching and pull-down to disable pwm switching. 34 ph_en i phase enable input (active high). pull-up to en able phase and pull-down to disable phase for current sharing. 35 cfg2 i, m configuration pin. sets the phase offset (singl e-phase) or current sharing group position (multi-phase). 36 pg o power-good output. epad sgnd pwr exposed thermal pad. common return for analog signals; internal connection to sgnd. connect to low impedance ground plane. notes: 1. i = input, o = output, pwr = power or ground. m = multi-mo de pin dependents. (refer to ?multi-mode pins? on page 11). 2. the sync pin can be used as a logic pin, a clock input or a clock output. 3. v dd is measured internally and the value is used to modify the pwm loop gain. pin descriptions (continued) pin label type (note 1) description ordering information part number (notes 5, 6) part marking temp. range (c) package (pb-free) pkg. dwg. # ZL6105alaf 6105 -40 to +85 36 ld qfn l36.6x6a ZL6105alaft (note 4) 6105 -40 to +85 36 ld qfn l36.6x6a ZL6105alaftk(note 4) 6105 -40 to +85 36 ld qfn l36.6x6a ZL6105alaf-01 6105-01 -40 to +85 36 ld qfn l36.6x6a ZL6105alaft-01 (note 4) 6105-01 -40 to +85 36 ld qfn l36.6x6a ZL6105alaftk-01 (note 4) 6105-01 -40 to +85 36 ld qfn l36.6x6a notes: 4. please refer to tb347 for details on reel specifications. 5. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 6. for moisture sensitivity level (msl), please see device information page for ZL6105 . for more information on msl please see techbrief tb363 .
ZL6105 6 fn6906.3 february 8, 2011 table of contents absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ZL6105 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 digital-dc architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power conversion overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power management overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 multi-mode pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power conversion functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 internal bias regulators and input supply connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 high-side driver boost circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 single resistor output voltage setting mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 smbus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 start-up procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 soft-start delay and ramp times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 switching frequency and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power train component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 current limit threshold selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 non-linear response (nlr ) settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 efficiency optimized driver dead-time cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 adaptive diode emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power management functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 input undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 output overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output pre-bias protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 thermal overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 voltage tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 voltage margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 i 2 c/smbus communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 i 2 c/smbus device address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 digital-dc bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 phase spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 output sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 fault spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 temperature monitoring using the xtemp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 active current sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 phase adding/dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 monitoring via i 2 c/smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 snapshot parameter capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 non-volatile memory and device security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ZL6105 7 fn6906.3 february 8, 2011 absolute maximum ratings (note 7) thermal information dc supply voltage for vdd pin . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 17v mosfet drive reference for vr pin @ 120ma . . . . . . . . . . . -0.3v to 6.5v 2.5v logic reference for v25 pin @ 120ma . . . . . . . . . . . . . . . -0.3v to 3v logic i/o voltage for cfg(0,1,2), ddc, en, fc(0, 1), ilim, mgn, pg, ph_en, sa(0, 1), salrt, scl, sda, ss, sync, uvlo, v(0,1) pins . . . . . . . . . . . . . . . . -0.3v to 6.5v analog input voltages for isenb, vsen, vtrk, xtemp pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v analog input voltages for isena pin . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v high side supply voltage for bst pin . . . . . . . . . . . . . . . . . . . . -0.3v to 30v boost to switch voltage for bst - sw pins . . . . . . . . . . . . . . . . . -0.3v to 8v high side drive voltage for gh pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(v sw - 0.3v) to (v bst + 0.3v) low side drive voltage for gl pin . . . . . . . . . . (pgnd - 0.3v) to vr + 0.3v switch node for sw pin continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(pgnd - 0.3v) to 30v transient (<100ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . (pgnd - 5v) to 30v ground voltage differential ( dgnd - sgnd, pgnd - sgnd ) for dgnd, sgnd and pgnd pins . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v esd rating human body model (note 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500v latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tested to jesd78 thermal resistance (typical) ja (c/w) jc (c/w) 36 ld qfn (notes 9, 10) . . . . . . . . . . . . . . . 35 5 operating junction temperature range . . . . . . . . . . . . . .-40c to +125c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions input supply voltage range, v dd (see figure 8) v dd tied to v r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0v to 5v v r floating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 14v output voltage range (v out ) (note 11) . . . . . . . . . . . . . . . . . . 0.54v to 5.5v junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 7. voltage measured with respect to sgnd. 8. bst, sw pins rated at 1.5kv. 9. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 10. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 11. includes margin limits. electrical specifications v dd = 12v, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. parameter conditions min (note 19) typ max (note 19) unit input and supply characteristics i dd supply current at f sw = 200khz gh, gl no load ? 16 30 ma i dd supply current at f sw = 1.4mhz ? 25 50 ma i dds shutdown current en = 0v no i 2 c/smbus activity ? 6.5 9 ma vr reference output voltage v dd > 6v, i vr < 20ma 4.5 5.2 5.5 v v25 reference output voltage v r > 3v, i v25 < 20ma 2.25 2.5 2.75 v output characteristics output voltage adjustment range (note 12) v in > v out 0.6 ? 5.0 v output voltage set-point resolution set using resistors ? 10 ? mv set using i 2 c/smbus ? 0.025 ? % fs (note 13) output voltage accuracy (note 14) includes line, load, temp -1 ? 1 % vsen input bias current vsen = 5.5v ? 110 200 a current sense differential input voltage (ground referenced) v isena -v isenb -100 ? 100 mv current sense differential input voltage (v out referenced, v out < 4.0v) v isena -v isenb -50 ? 50 mv current sense input bias current ground referenced -100 ? 100 a
ZL6105 8 fn6906.3 february 8, 2011 current sense input bias current (v out referenced, v out < 4.0v) isena -1 ? 1 a isenb -100 ? 100 a soft-start delay duration range se t using ss pin or resistor (note 15) 5 ? 30 ms set using i 2 c/smbus (note 15) 0.005 ? 500 s soft-start delay duration accuracy turn-on delay (note 15) - -0.25/+4 - ms turn-off delay (note 15) - -0.25/+4 - ms soft-start ramp duration range set using ss pin or resistor 2 ? 20 ms set using i 2 c 0 ? 200 ms soft-start ramp duration accuracy ? 100 ? s logic input/output characteristics logic input leakage current en, scl, sda pins -250 ? 250 na logic input low, v il ? ? 0.8 v logic input open (n/c )multi-mode logic pins ? 1.4 ? v logic input high, v ih 2.0 ? ? v logic output low, v ol i ol 4ma (note 20) ? ? 0.4 v logic output high, v oh i oh -2ma (note 20) 2.25 ? ? v oscillator and switching characteristics switching frequency range 200 ? 1400 khz switching frequency set-point accuracy predefined settings (see table 11) -5 ? 5 % maximum pwm duty cycle factory default 95 ? ? % minimum sync pulse width 150 ? ? ns input clock frequency drift tolerance external clock source -13 ? 13 % gate drivers high-side driver voltage (v bst -v sw ) ? 4.5 ? v high-side driver peak gate drive current (pull-down) (v bst -v sw ) = 4.5v 2 3 ? a high-side driver pull-up resistance (v bst -v sw ) = 4.5v, (v bst -v gh ) = 50mv ? 0.8 2 high-side driver pull-down resistance (v bst -v sw ) = 4.5v, (v gh -v sw ) = 50mv ? 0.5 2 low-side driver peak gate drive current (pull-up) v r = 5v ? 2.5 ? a low-side driver peak gate drive current (pull-down) v r = 5v ? 1.8 ? a low-side driver pull-up resistance v r = 5v, (v r -v gl ) = 50mv ? 1.2 2 low-side driver pull-down resistance v r = 5v, (v gl -pgnd) = 50mv ? 0.5 2 switching timing gh rise and fall time gl rise and fall time (v bst -v sw ) = 4.5v, c load = 2.2nf ? 5 20 ns v r = 5v, c load = 2.2nf ? 5 20 ns tracking vtrk input bias current vtrk = 5.5v ? 110 200 a vtrk tracking ramp accuracy 100% tracking, v out -vtrk, no prebias -100 ? + 100 mv vtrk regulation accuracy 100% tracking, v out -vtrk -1 ? 1 % fault protection characteristics uvlo threshold range configurable via i 2 c/smbus 2.85 ? 16 v uvlo set-point accuracy -150 ? 150 mv uvlo hysteresis factory default ? 3 ? % configurable via i 2 c/smbus 0 ? 100 % electrical specifications v dd = 12v, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 19) typ max (note 19) unit
ZL6105 9 fn6906.3 february 8, 2011 uvlo delay ? 2.5 - s power good v out threshold factory default ? 90 ? % v out power good v out hysteresis factory default ? 5 ? % power good delay using pin-strap or resistor (note 16) 0 ? 200 ms configurable via i 2 c/smbus 0 ? 500 s vsen undervoltage threshold factory default ? 85 ? % v out configurable via i 2 c/smbus 0 ? 110 % v out vsen overvoltage threshold factory default ? 115 ? % v out configurable via i 2 c/smbus 0 ? 115 % v out vsen undervoltage hysteresis ? 5 ? % v out vsen undervoltage/overvoltage fault response time factory default ? 16 ? s configurable via i 2 c/smbus 5 ? 60 s current limit set-point accuracy (v out referenced) ? 10 ? % fs (note 17) current limit set-point accuracy (ground referenced) ? 10 ? % fs (note 17) current limit protection delay factory default ? 10 ? t sw (note 18) configurable via i 2 c/smbus 1 ? 32 t sw (note 18) temperature compensation of current limit protection threshold factory default 4400 ppm/c configurable via i 2 c/smbus 100 12700 thermal protection threshold (junction temperature) factory default ? 125 ? c configurable via i 2 c/smbus -40 ? 125 c thermal protection hysteresis ? 15 ? c notes: 12. does not include margin limits. 13. percentage of full scale (fs) with temperature compensation applied. 14. v out measured at the termination of the vsen+ and vsen-sense points. 15. the device requires a minimum delay period following an enable signal and prior to ramping its output as described in ?soft- start delay and ramp times? on page 14. 16. factory default power good delay is set to the same value as the soft-start ramp time. refer to ?soft-start delay and ramp t imes? on page 14 for further restrictions on pg delay. 17. percentage of full scale (fs) with temperature compensation applied 18. t sw = 1/f sw , where f sw is the switching frequency. 19. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 20. nominal capacitance of logic pins is 5pf. electrical specifications v dd = 12v, t a = -40c to +85c unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter conditions min (note 19) typ max (note 19) unit
ZL6105 10 fn6906.3 february 8, 2011 ZL6105 overview digital-dc architecture the ZL6105 is an innovative mixed-signal power conversion and power management ic based on zilker labs patented digital-dc technology that provides an integrated, high performance step-down converter for a wide variety of power supply applications. today?s embedded power systems ar e typically designed for optimal efficiency at maximum load, reducing the peak thermal stress by limiting the total thermal di ssipation inside the system. unfortunately, many of these systems are often operated at load levels far below the peak where the power system has been optimized, resulting in reduced efficiency. while this may not cause thermal stress to occur, it does cont ribute to higher electricity usage and results in higher overall system operating costs. zilker labs? efficiency-adaptive ZL6105 dc/dc controller helps mitigate this scenario by enabling the power converter to automatically change their operatin g state to increase efficiency and overall performance with little or no user interaction needed. auto compensation is available to eliminate the need for manual compensation of the pid filter. its unique pwm loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required , resulting in a very flexible device that is also very easy to use. an extensive set of power management functions are fu lly integrated and can be configured using simple pin conn ections. the user configuration can be saved in an internal non-volatile memory (nvm). additionally, all functions can be configured and monitored via the smbus hardware interface using standard pmbus commands, allowing ultimate flexibility. once enabled, the ZL6105 is im mediately ready to regulate power and perform power management tasks with no programming required. advanced configuration options and real-time configuration chan ges are available via the i 2 c/smbus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. integrated sub-re gulation circuitry enables single supply operation from any supply between 3v and 14v with no secondary bias supplies needed. the ZL6105 can be configured by simply connecting its pins according to the tables provid ed in the following sections. additionally, a comprehensive set of development tools and application notes are available to help simplify the design process. an evaluation board is also available to help the user become familiar with the device. this board can be evaluated as a standalone platform using pin configuration settings. a windows? based gui is also provided to enable full configuration and monitoring capability via the i 2 c/smbus interface using an available computer and the included usb cable. application notes are available to assist the user in designing to specific application demands. please visit www.intersil.com to access the most up-to-date documentation. power conversion overview the ZL6105 operates as a voltage-mode, synchronous buck converter with a selectable co nstant frequency pulse width modulator (pwm) control scheme that uses external mosfets, capacitors, and an inductor to perform power conversion. figure 5 illustrates the basic synchronous buck converter topology showing the primary power train components. this converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. in its most simple configuration, the ZL6105 requires two external n-channel power mosfets, one for the top control mosfet (qh) and one for the bottom synchronous mosfet (ql). the amount of time that qh is on as a fraction of the total switching period is known as the duty cycle d , which is described by equation 1: during time d, qh is on and v in ? v out is applied across the inductor. the current ramps up as shown in figure 6. when qh turns off (time 1-d), the current flowing in the inductor must continue to flow from th e ground up through ql, during which the current ramps down. since the output capacitor c out exhibits a low impedance at the switching frequency, the ac component of the inductor current is filtered from the output voltage so the load sees nearly a dc voltage. typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage. this duty cycle limit ensures that the low-side mosfet is allowed to turn on for a minimum amount of time during each switching cycl e, which enables the bootstrap capacitor (cb in figure 6) to be charged up and provide adequate v in v out gh gl zl sw vr bst qh ql cb db c out c in figure 5. synchronous buck converter in out v v d (eq. 1) figure 6. inductor waveform voltage (v) time d 1 - d 0 v in - v out -v out current (a) il pk i o il v
ZL6105 11 fn6906.3 february 8, 2011 gate drive voltage for the high-side mosfet. see ?high-side driver boost circuit? on page 12 for more details. in general, the size of components l1 and c out as well as the overall efficiency of the circuit are inversely proportional to the switching frequency, f sw . therefore, the highest efficiency circuit may be realized by switching the mosfets at the lowest possible frequency; however, this will result in the largest component size. conversely, the smallest possible footprint may be realized by switching at the fastest possible frequency but this gives a somewhat lower efficiency. each user should determine the optimal combination of size and efficiency when determining the switching frequency for each application. the block diagram for the ZL6105 is illustrated in figure 4. in this circuit, the target output voltag e is regulated by connecting the differential vsen pins directly to the output regulation point. the vsen signal is then compared to a reference voltage that has been set to the desired output voltage level by the user. the error signal derived from this comparison is converted to a digital value with a low-resolution, analog to digital (a/d) converter. the digital signal is applied to an adjustable digital compensation filter, and the compensated signal is used to derive the appropriate pwm duty cycle for dr iving the external mosfets in a way that produces the desired output. the ZL6105 has several features to improve the power conversion efficiency. a non-linear response (nlr) loop improves the response time and reduces the output deviation as a result of a load transient. the ZL6105 monitors the power converter?s operating conditions and continuously adjusts the turn-on and turn-off timing of the high-side and low-side mosfets to optimize the overall efficiency of the power supply. adaptive performance optimization algorithms such as dead-time control, diode emulation, and frequency control are available to provide greater efficiency improvement. power management overview the ZL6105 incorporates a wide range of configurable power management features that are simple to implement with no external components. additiona lly, the ZL6105 includes circuit protection features that contin uously safeguard the device and load from damage due to unexpected system faults. the ZL6105 can continuously monitor input voltage, output voltage/current, internal temperature, and the temperature of an external thermal diode. a power-good output signal is also included to enable power-on reset functionality for an external processor. all power management functions ca n be configured using either pin configuration techniques (s ee figure 8) or via the i 2 c/smbus interface. monitoring parameters can also be pre-configured to provide alerts for specific conditions. see application note an2033 for more details on smbus monitoring. multi-mode pins in order to simplify circuit design, the ZL6105 incorporates patented multi-mode pins that allow the user to easily configure many aspects of the device with no programming. most power management features can be configured using these pins. the multi-mode pins can respond to fo ur different connections as shown in table 1. these pins are sampled when power is applied or by issuing a pmbus restore command (see application note an2033). pin-strap settings this is the simplest implementation method, as no external components are required. using th is method, each pin can take on one of three possible states: low, open, or high. these pins can be connected to the v25 pin for logic high settings as this pin provides a regulated voltage higher than 2v. using a single pin, one of three settings can be selected. using two pins, one of nine settings ca n be selected. resistor settings this method allows a greater rang e of adjustabilit y when connecting a finite value resistor (in a specified range) between the multi-mode pin and sgnd. standard 1% resistor values are used, and only every fourth e96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. up to 31 unique selections are available using a single resistor. i 2 c/smbus method almost any ZL6105 function can be configured via the i 2 c/smbus interface using standard pmbus commands. additionally, any value that has been configured using th e pin-strap or resistor setting methods can also be re-configu red and/or verified via the i 2 c/smbus. see application no te an2033 for more details. the smbus device address and vout_max are the only parameters that must be set by external pins. all other device parameters can be set via the i 2 c/smbus. the device address is set using the sa0 and sa1 pins. vout_max is determined as 10% greater than the voltage set by the v0 and v1 pins. table 1. multi-mode pin configuration pin tied to value low (logic low) < 0.8 vdc open (n/c) no connection high (logic high) > 2.0 vdc resistor to sgnd set by resistor value zl multi-mode pin zl r set logic high logic low open pin-strap settings resistor settings multi-mode pin figure 7. pin-strap and resistor setting examples
ZL6105 12 fn6906.3 february 8, 2011 power conversion functional description internal bias regulators and input supply connections the ZL6105 employs two internal low dropout (ldo) regulators to supply bias voltages for internal circuitry, allowing it to operate from a single input supply. the in ternal bias regulators are as indicated in the following: vr - the vr ldo provides a regulated 5v bias supply for the mosfet driver circuits. it is powered from the vdd pin. a 4.7f filter capacitor is required at the vr pin. v25 - the v25 ldo provides a regulated 2.5v bias supply for the main controller circuitry. it is powered from an internal 5v node. a 10f filter capacitor is required at the v25 pin. when the input supply (vdd) is higher than 5.5v, the vr pin should not be connected to any other pins. it should only have a filter capacitor attached as shown in figure 8. due to the dropout voltage associated with the vr bias re gulator, the vdd pin must be connected to the vr pin for designs operating from a supply below 5.5v. figure 8 illustrates the required connections for both cases. note : the internal bias regulators are not designed to be outputs for powering other circuitry. do not attach external loads to any of these pins. the multi-mode pins may be connected to the v25 pin for logic high settings. high-side driver boost circuit the gate drive voltage for the high-side mosfet driver is generated by a floating bootstrap capacitor, cb (see figure 5). when the lower mosfet (ql) is turned on, the sw node is pulled to ground and the capacitor is charged from the internal vr bias regulator through diode db. when ql turns off and the upper mosfet (qh) turns on, the sw node is pulled up to v dd and the voltage on the bootstrap capacitor is boosted approximately 5v above v dd to provide the necessary voltage to power the high-side driver. a schottky diode should be used for db to help maximize the high-side drive supply voltage. output voltage selection standard mode the output voltage may be set to any voltage between 0.6v and 5.0v provided that the input volt age is higher than the desired output voltage by an amount su fficient to prevent the device from exceeding its maximum duty cycle specification. using the pin-strap method, v out can be set to any of nine standard voltages as shown in table 2. the resistor setting method can be used to set the output voltage to levels not available in table 2. resistors r 0 and r 1 are selected to produce a specific voltage between 0.6v and 5.0v in 10mv steps. resistor r 1 provides a coarse setting and resistor r 0 provides a fine adjustment, th us eliminating the additional errors associated with using two 1% resistors (this typically adds approximately 1.4% error). to set v out using resistors, follow the steps indicated to calculate an index value and then use table 3 to select the resistor that corresponds to the calculated index value as follows: 1. calculate index1: 2. round the result down to the nearest whole number. 3. select the value of r 1 from table 3 using the index1 rounded value from step 2. 4. calculate index0: 5. select the value of r 0 from table 3 using the index0 value from step 4. example from figure 9: for v out = 1.33v, index1 = 4 x 1.33v = 5.32; from table 3, r 1 = 16.2k index0 = (100 x 1.33v) ? (25 x 5) = 8; from table 3, r 0 = 21.5k v in vdd vr zl v in vdd vr zl 3v v in 5.5v 5.5v ZL6105 13 fn6906.3 february 8, 2011 the output voltage can be determined from the r 0 (index0) and r 1 (index1) values using equation 4: single resistor output voltage setting mode some applications desire the ou tput voltage to be set using a single resistor. this can be acco mplished using a resistor on the v1 pin while the v0 pin is tied to sgnd. table 4 lists the available output voltage settings with a single resistor. smbus mode the output voltage may be set to any value between 0.6v and 5.0v using a pmbus command over the i 2 c/smbus interface. see application note an2033 for details. start-up procedure the ZL6105 follows a specific in ternal start-up procedure after power is applied to the vdd pin. table 5 describes the start-up sequence. if the device is to be synchronized to an external clock source, the clock frequency must be stable pr ior to asserting the en pin. the device requires approximately 5ms to 10ms to check for specific values stored in its internal memory. if the user has stored values in memory, those values will be loaded. the device will then check the status of all multi-mode pins and load the values associated with the pin settings. once this process is completed, the device is ready to accept commands via the i 2 c/smbus interface and the device is ready to be enabled. once enabled, the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ?soft-start delay and ramp times? on page 14. if a soft-start delay pe riod less than the minimum has been configured (using pmbu s commands), the device will default to the minimum delay period. if a delay period greater than the minimum is configured, the device will wait for the configured delay period prior to starting to ramp its output. after the delay period has expired, the output will begin to ramp towards its target voltage according to the pre-configured soft- start ramp time that has been set using the ss pin. it should be noted that if the en pin is tied to vdd, the device will still require approximately 5ms to 10ms befo re the output can begin its ramp-up as described in table 5. table 4. single resistor v out setting r v1 (k ? )r v0 v out 10 low 0.60 11 low 0.65 12.1 low 0.70 13.3 low 0.75 14.7 low 0.80 16.2 low 0.85 17.8 low 0.90 19.6 low 0.95 21.5 low 1.00 23.7 low 1.05 26.1 low 1.10 28.7 low 1.15 31.6 low 1.20 34.8 low 1.25 38.3 low 1.30 42.2 low 1.40 46.4 low 1.50 51.1 low 1.60 56.2 low 1.70 61.9 low 1.80 68.1 low 1.90 75 low 2.00 82.5 low 2.10 90.9 low 2.20 100 low 2.30 110 low 2.50 121 low 3.00 100 ) 1 25 ( 0 index index v out + = (eq. 4) 133 low 3.30 147 low 4.00 162 low 5.00 178 low 5.50 table 4. single resistor v out setting (continued) r v1 (k ? )r v0 v out v in v out 1.33v gh gl zl sw v0 r0 21. 5 k ? v1 r1 16 .2 k ? figure 9. output voltage resistor setting example
ZL6105 14 fn6906.3 february 8, 2011 soft-start delay and ramp times it may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. in addition, the designer may wish to precisely set the time required for v out to ramp to its target value after the delay period has expired. these features may be used as part of an overall inrush current management strategy or to precisely control how fast a load ic is turned on. the ZL6105 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. the soft-start delay period begins when the en pin is asserted and ends when the delay time expires. the soft-start delay period is set using the ss pin. the soft-start ramp timer enables a precisely controlled ramp to the nominal v out value that begins once the delay period has expired. the ramp-up is guaranteed monotonic and its slope may be precisely set using the ss pin. the soft start delay and ramp times can be set to standard values according to table 6. if the desired soft-start delay and ramp times are not one of the values listed in table 6, the times can be set to a custom value by connecting a resistor from the ss pi n to sgnd using the appropriate resistor value from table 7. the value of this resistor is measured upon start-up or restore and will not change if the resi stor is varied after power has been applied to the ZL6105. the soft-start delay and ramp times can also be set to custom values via the i 2 c/smbus interface. when the ss delay time is set to 0ms, the device will begi n its ramp-up after the internal circuitry has initialized (approximately 2ms). when the soft-start ramp period is set to 0ms, the output will ramp up as quickly as the output load capacitance and loop settings will allow. it is generally recommended to set th e soft-start ramp to a value greater than 500s to prevent inad vertent fault conditions due to excessive in-rush current. the ZL6105 has a minimum ton_delay requirement that is a function of the operating mode. table 8 shows the different mode configurations and the minimum ton_delay required for each mode. current sharing is configured with the ishare_config pmbus command, auto compensation is configured with the auto_comp_config command, and standby mode is configured as low power with the user_config command. see application note an2033 for details. table 5. ZL6105 start-up sequence step # step name description time duration 1 power applied input voltage is applied to the ZL6105?s vdd pin depends on input supply ramp time 2 internal memory check the device will check for va lues stored in its internal memory. this step is also performed after a restore command. approximately 5ms to 10ms (device will ignore an enable signal or pmbus traffic during this period) 3 multi-mode pin check the device loads valu es configured by the multi-mode pins. 4 device ready the device is ready to accept an enable signal. ? 5 pre-ramp delay the device requires a minimum delay period following an enable signal and prior to ramping its output, as described in ?soft-start delay and ramp times? on page 14. ? table 6. soft-start pin-strap settings ss pin delay time (ms) ramp time (ms) low 5 2 open 5 5 high 10 10 table 7. ss resistor settings r ss (k ) delay time (ms) ramp time (ms) 13.3 5 2 14.7 5 16.2 10 17.8 20 19.6 10 2 21.5 5 23.7 10 26.1 20 28.7 15 2 31.6 5 34.8 10 38.3 20 42.2 20 2 46.4 5 51.1 10 56.2 20 61.9 30 2 68.1 5 75 10 82.5 20
ZL6105 15 fn6906.3 february 8, 2011 power-good the ZL6105 provides a power-good (p g) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. by de fault, the pg pin will assert if the output is within -10% of the target voltage. these limits and the polarity of the pin may be changed via the i 2 c/smbus interface. see application note an2033 for details. a pg delay period is defined as the time from when all conditions within the ZL6105 for asserting pg are met to when the pg pin is actually asserted. this feature is commonly used instead of using an external reset controller to control external digital logic. by default, the ZL6105 pg delay is set equal to the soft-start ramp time setting. therefore, if the soft-start ramp time is set to 10ms, the pg delay will be set to 10ms. the pg delay may be set independently of the soft-start ramp using the i 2 c/smbus as described in application note an2033. if auto comp is enabled, the pg timing is further controlled by the pg assert parameter, as described in ?loop compensation? on page 21. switching frequency and pll the ZL6105 incorporates an internal phase-locked loop (pll) to clock the internal circuitry. the pll can be driven by an external clock source connected to the sync pin. when usin g the internal oscillator, the sync pin can be configured as a clock source for other zilker labs devices. the sync pin is a unique pin that can perform multiple functions depending on how it is configured. the cfg1 pin is used to select the operating mode of the sync pin as shown in table 9. figure 13 illustrates the typical connections for each mode. configuration a: sync output when the sync pin is configured as an output (cfg1 pin is tied high), the device will run from its internal oscillator and will drive the resulting internal oscillator signal (preset to 400khz) onto the sync pin so other devices can be synchronized to it. the sync pin will not be checked for an incoming clock signal while in this mode. configuration b: sync input when the sync pin is configured as an input (cfg1 pin is tied low) and the device is in monitor mode or self-enabled (en tied to v25 or on_off_config[4] = 0), the device will check for a clock signal on the sync pin immediately after power-up. in this case, the incoming clock signal must be in the range of 200khz to 1.4mhz and must be stable within 10s after v25 rises above 2.25v. when the sync pin is configured as an input (cfg1 pin is tied low) and the device is in low power mode, the device will check for a clock signal on the sync pin immediately after en goes true. in th is case, the incoming clock signal must be in range and stable before en goes true. the ZL6105's oscillator will then synchronize with th e rising edge of the external clock. the incoming clock signal must be in the range of 200khz to 1.4mhz and must be stable when the enable pin is asserted. the clock signal must also exhi bit the necessary performance requirements (see ?electrical specifications? on page 8). in the event of a loss of the external clock signal, the output voltage may show transient over/undershoot. if this happens, the ZL6105 wi ll automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. configuration c: sync auto detect when the sync pin is configured in auto detect mode (cfg1 pin is left open) and the device is in monitor mo de or self-enabled (en tied to v25 or on_off_config[4] = 0), the device will check for a clock signal on the sync pin immediately after power-up. in this case, the incoming clock signal must be in the range of 200khz to 1.4mhz and must be stable within 10s after v25 rises above 2.25v. when the sync pin is configured in auto detect mode (cfg1 pin is left open) and the device is in low power mode, the device will check for a clock signal on the sync pin immediately after en goes true. in this case, the incoming clock signal must be in range and stable before en goes true. if a clock signal is present, the ZL6105's oscillator will then synchronize with the rising edge of the external clock. refer to ?configuration b: sync input? in the preceding section. if no incoming clock signal is present, the ZL6105 will configure the switching frequency according to the state of the sync pin as listed in table 10. in sync autodetect mode, the ZL6105 will only read the sync pin connect ion during the first start-up sequence; changes to sync pin connections will not affect f sw until the power (vdd) is cycled off and on. if the user wishes to run the ZL6105 at a frequency not listed in figure 10, the switching frequency can be set using an external resistor, r sync , connected between sync and sgnd using table 11. table 8. minimum ton delay vs operating mode current sharing autocomp low-power standby min. ton_delay (ms) x disabled false 5 disabled enabled false 5 disabled x true 10 enabled disabled true 15 enabled enabled x 15 table 9. sync pin function selection cfg1 pin sync pin function low sync is configured as an input open auto detect mode high sync is config ured as an output f sw = 400khz table 10. switching frequency pin-strap settings sync pin frequency low 200khz open 400khz high 1mhz resistor see table 11
ZL6105 16 fn6906.3 february 8, 2011 the switching frequency can also be set to any value between 200khz and 1.33mhz using the i 2 c/smbus interface. the available frequencies below 1.4mhz are defined by f sw = 8mhz/n, where the whole number n is 6 n 40. see application note an2033 for details. if a value other than f sw = 8mhz/n is entered using a pmbus command, the internal circuitry will select the valid switching frequency value that is closest to the entered value. for example, if 810khz is entered, the device will select 800khz (n = 10). when multiple zilker labs devices are used together, connecting the sync pins together will force all devices to synchronize with each other. the cfg1 pin of one device must set its sync pin as an output and the remaining devices must have their sync pins set as auto detect. note : the switching frequency read back using the appropriate pmbus command will differ slightly from the selected values in table 11. the difference is due to hardware quantization. power train component selection the ZL6105 is a synchronous buck converter that uses external mosfets, inductor and capacitors to perform the power conversion process. the proper selection of the external components is critical for optimized performance. to select the appropriate external components for the desired performance goals, the power supply requirements listed in table 12 must be known. design goal trade-offs the design of the buck power stage requires several compromises among size, efficiency, and cost. the inductor core loss increases with frequency, so there is a trade-off between a small output filter made possible by a higher switching frequency and getting better power supply efficiency. size can be decreased zl logic high cfg1 sync 200 khz ? 1.33mhz zl cfg1 sync 200khz ? 1.4mhz zl n/ c cfg1 sync 200khz ? 1.4mhz a) sync = output b) sync = input zl n/ c cfg1 sync zl r syn c n/ c cfg1 sync logic high logic low open c) sync = auto detect or or figure 10. sync pin configurations table 11. switching freq uency resistor settings r sync (k ) f sw (k hz ) r sync (k ) f sw (k hz ) 10 200 26.1 533 11 222 28.7 571 12.1 242 31.6 615 13.3 267 34.8 727 14.7 296 38.3 800 16.2 320 46.4 889 17.8 364 51.1 1000 19.6 400 56.2 1143 21.5 421 68.1 1333 23.7 471 table 12. power supply requirements parameter range example value input voltage (v in ) 3v to 14v 12v output voltage (v out ) 0.6v to 5.0v 1.2v output current (i out ) 0a to ~25a 20a output voltage ripple (v orip ) <3% of v out 1% of v out output load step (i ostep ) ZL6105 17 fn6906.3 february 8, 2011 by increasing the switching frequency at the expense of efficiency. cost can be minimized by using through-hole inductors and capacitors; however these components are physically large. to start the design, select a sw itching frequency based on table 13. this frequency is a starting point and may be adjusted as the design progresses. inductor selection the output inductor selection process must include several trade-offs. a high inductance value will result in a low ripple current (i o(p-p) ), which will reduce output capacitance and produce a low output ripple voltage, but may also compromise output transient load performance. therefore, a balance must be struck between output ripple and optimal load transient performance. a good starting point is to select the output inductor ripple equal to the expected load transient step magnitude (i ostep ) as shown in equation 5: now the output inductance can be calculated using equation 6: where v inm is the maximum input voltage. the average inductor current is equal to the maximum output current. the peak inductor current (i lpk ) is calculated using equation 7: where i out is the maximum output current. select an inductor rated for the average dc current with a peak current rating above the peak current computed in equation 7. in overcurrent or short-circuit conditions, the inductor may have currents greater than 2x the normal maximum rated output current. it is desirable to use an inductor that still provides some inductance to protect the load and the mosfets from damaging currents in this situation. once an inductor is selected, the dcr and core losses in the inductor are calculated as in equation 8. use the dcr specified in the inductor manufacturer?s datasheet. i lrms is given by equation 9. where i out is the maximum output current. next, calculate the core loss of the selected inductor. since this calculation is specific to each inductor and manufacturer, refer to the chosen inductor datasheet. add the core loss and the esr loss and compare the total loss to th e maximum power dissipation recommendation in the inductor datasheet. output capacitor selection several trade-offs must also be considered when selecting an output capacitor. low esr values are needed to have a small output deviation during transient load steps (v osag ) and low output voltage ripple (v orip ). however, capacitors with low esr, such as semi-stable (x5r and x7r) dielectric ceramic capacitors, also have relatively low capacitance values. many designs can use a combination of high capacitance devices and low esr devices in parallel. for high ripple currents, a low capacitance value can cause a significant amount of output voltage ripple. likewise, in high transient load steps, a relatively large amount of capacitance is needed to minimize the output voltage deviation while the inductor current ramps up or down to the new steady state output current value. as a starting point, apportion one-half of the output ripple voltage to the capacitor esr and the other half to capacitance, as shown in the equations 10 and 11: use these values to make an init ial capacitor selection, using a single capacitor or several capacitors in parallel. after a capacitor has been selected, the resulting output voltage ripple can be calculated using equation 12: because each part of this equation was made to be less than or equal to half of the allowed output ripple voltage, the v orip should be less than the desi red maximum output ripple. input capacitor it is highly recommended that dedicated input capacitors be used in any point-of-load design, even when the supply is powered from a heavily filtered 5v or 12v ?bulk? supply from an off-line power supply. this is because of the high rms ripple current that is drawn by the buck converter topology. this ripple (i cinrms ) can be determined from equation 13: table 13. circuit design considerations frequency range efficiency circuit size 200khz to 400khz highest larger 400khz to 800khz moderate smaller 800khz to 1.4mhz lower smallest ostep opp i i = (eq. 5) opp inm out out out i fsw v v v l ? ? ? ? ? ? ? ? ? = 1 (eq. 6) 2 opp out lpk i i i + = (eq. 7) 2 lrms ldcr i dcr p = (eq. 8) () 12 2 2 opp out lrms i i i + = (eq. 9) 2 8 orip sw opp out v f i c = (eq. 10) opp orip i v esr = 2 (eq. 11) out sw opp opp orip c f i esr i v + = 8 (eq. 12) ) 1 ( d d i i out cinrms ? = (eq. 13)
ZL6105 18 fn6906.3 february 8, 2011 without capacitive filtering near the power supply circuit, this current would flow through the supply bus and return planes, coupling noise into other system circuitry. the input capacitors should be rated at 1.2x the ripple current calculated in equation 13 to avoid overheating of the capacitors due to the high ripple current, which can cause premature failure. ceramic capacitors with x7r or x5r dielectric with low esr and 1.1x the maximum expected input voltage are recommended. bootstrap capacitor selection the high-side driver boost circuit utilizes an external schottky diode (d b ) and an external bootstrap capacitor (c b ) to supply sufficient gate drive for the high-side mosfet driver. d b should be a 20ma, 30v schottky diode or equivalent device and c b should be a 1f ceramic type rated for at least 6.3v. ql selection the bottom mosfet should be se lected primarily based on the device?s r ds(on) and secondarily based on its gate charge. to choose ql, use equation 14 and allow 2% to 5% of the output power to be dissipated in the r ds(on) of ql (lower output voltages and higher step-down ratios will be closer to 5%): calculate the rms current in ql as shown in equation 15: calculate the desired maximum r ds(on) as shown in equation 16: note that the r ds(on) given in the manufacturer?s datasheet is measured at +25c. the actual r ds(on) in the end-use application will be much higher. for example, a vishay si7114 mosfet with a junction temperature of +125c has an r ds(on) that is 1.4x higher than the value at +25c. select a candidate mosfet, and calculate the required gate drive current as shown in equation 17: keep in mind that the total allowe d gate drive current for both qh and ql is 80ma. mosfets with lower r ds(on) tend to have higher gate charge requirements, which increases the current and resulting power required to turn them on and off. since the mosfet gate drive circuits are integrated in the ZL6105, this power is dissipated in the ZL6105 according to the equation 18: qh selection in addition to the r ds(on) loss and gate charge loss, qh also has switching loss. the procedure to select qh is similar to the procedure for ql. first, assign 2% to 5% of the output power to be dissipated in the r ds(on) of qh using equation 18 for ql. as was done with ql, calculate the rms current as shown in equation 19: calculate a starting r ds(on) as shown in equation 20. this equation uses 5% as an example: select a mosfet and calculate the resulting gate drive current. verify that the combined gate drive current from ql and qh does not exceed 80ma. next, calculate the switching time using equation 22: where q g is the gate charge of the selected qh and i gdr is the peak gate drive current available from the ZL6105. although the ZL6105 has a typical gate drive current of 3a, use the minimum guaranteed current of 2a for a conservative design. using the calculated switching time, calculate the switching power loss in qh using equation 23: the total power dissipated by qh is given by equation 24: mosfet thermal check once the power dissipations for qh and ql have been calculated, the mosfets junction temperature can be estimated. using the junction-to-case thermal resistance (r th ) given in the mosfet manufacturer?s datasheet and the expected maximum printed circuit board temperature, calcul ate the junction temperature as shown in equation 25: current sensing components once the current sense method has been selected (refer to ?current limit threshold selection? on page 19?), the components are selected as indicated in the following. when using the inductor dcr sensing method, the user must also select an r/c network co mprised of r1 and cl (see figure 11). out out ql i v p = 05 . 0 (eq. 14) d i i lrms botrms ? = 1 (eq. 15) () 2 ) ( botrms ql on ds i p r = (eq. 16) g sw g q f i = (eq. 17) inm g sw ql v q f p = (eq. 18) d i i lrms toprms = (eq. 19) out out qh i v p = 05 . 0 (eq. 20) () 2 ) ( toprms qh on ds i p r = (eq. 21) gdr g sw i q t = (eq. 22) sw out sw inm swtop f i t v p = (eq. 23) swtop qh qhtot p p p + = (eq. 24) () th q pcb j r p t t + = max (eq. 25) gh gl isena zl isenb sw r1 cl r2 figure 11. dcr current sensing
ZL6105 19 fn6906.3 february 8, 2011 for the voltage across c l to reflect the voltage across the dcr of the inductor, the time constant of the inductor must match the time constant of the rc network as shown in equation 26: for l, use the average of the nominal value and the minimum value. include the effects of tolerance, dc bias and switching frequency on the inductance when determining the minimum value of l. use the typical value for dcr. the value of r 1 should be as small as feasible and no greater than 5k for best signal-to-noise ra tio. the designer should make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. in calculating the minimum value of r 1 , the average voltage across c l (which is the average i out dcr product) is small and can be neglected. therefore, the minimum value of r 1 may be approximated by equation 27: where p r1pkg- max is the maximum power dissipation specification for the resistor package and p is the derating factor for the same parameter (eg: p r1pkg- max = 0.0625w for 0603 package, p = 50% @ +85c). once r 1- min has been calculated, solve for the maximum value of c l from equation 28: next, choose the next-lowest re adily available value (eg: for c l- max = 1.86f, c l = 1.5f is a good choice). then substitute the chosen value into the same equation and re-calculate the value of r 1 . choose the 1% resistor stan dard value closest to this re-calculated value of r 1 . the error due to the mismatch of the two time constants is as shown in equation 29. the value of r 2 should be simply 5x that of r 1 as shown in equation 30: for the r ds(on) current sensing method, the external low side mosfet will act as the sensing element as indicated in figure 12. current limit threshold selection it is recommended that the user include a current limiting mechanism in their design to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is shorted to ground or an overload condition is imposed on the output. current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. output current sensing can be accomplished by measuring the voltage across a series resistiv e sensing element according to equation 31: where: i lim is the desired maximum curren t that should flow in the circuit. r sense is the resistance of the sensing element. v lim is the voltage across the sensing element at the point the circuit should start limiting the output current. the ZL6105 supports ?lossless? current sensing by measuring the voltage across a resistive element that is already present in the circuit. this eliminates addi tional efficiency losses incurred by devices that must use an addi tional series resistance in the circuit. to set the current limit threshold, the user must first select a current sensing method. the ZL6105 incorporates two methods for current sensing, synchronous mosfet r ds(on) sensing and inductor dc resistance (dcr) sensing; figure 12 shows a simplified schematic for each method. the current sensing method can be selected via the i 2 c/smbus interface. please refer to application no te an2033 for details. dcr l c r l dcr l rc = ? = 1 / (eq. 26) ()() p pkg r out out in p v d v v d r ? ? ? + ? = ? ? ? max 1 2 2 max min 1 1 (eq. 27) dcr r l c l ? = ? ? min 1 max (eq. 28) % 100 1 1 ? ? ? ? ? ? ? ? ? ? ? ? = avg l l dcr c r (eq. 29) 1 2 5 r r ? = (eq. 30) v in v out gh gl isena zl isenb sw inductor dcr sensing (v out must be less than 4.0 v) v in v out gh gl isena zl isenb sw mosfet r ds(on) sensing figure 12. current sensing methods sense lim lim r i v = (eq. 31)
ZL6105 20 fn6906.3 february 8, 2011 in addition to selecting the cu rrent sensing method, the ZL6105 gives the power supply designer several choices for the fault response during over or under current condition. the user can select the number of violations allowed before declaring fault, a blanking time and the action ta ken when a fault is detected. the blanking time represents the time when no current measurement is taken. this is to avoid taking a reading just after a current load step (less accurate due to potential ringing). it is a configurable parameter. once the sensing method has been selected, the user must select the voltage threshold (v lim), the desired current limit threshold, and the resistance of the sensing element. the current limit threshold voltag e can be selected by simply connecting the ilim pin as shown in table 14. the ground-referenced sensing method is being used in this mode. note that iout_cal_gain is set to 2m for rds sensing and set to 1m for dcr sensing by default. the threshold voltage can also be selected in 5mv increments by connecting a resistor, r lim , between the ilim pin and ground according to table 15. this method is preferred if the user does not desire to use or does not have access to the i 2 c/smbus interface and the desired threshold value is contained in table 15. the current limit threshold can also be set to a custom value via the i 2 c/smbus interface. please refer to application note an2033 for further details. table 14. current limit threshold voltage pin-strap settings ilim pin r ds v lim (mv) dcr v lim (mv) low 50 25 open 60 30 high 70 35 table 15. current limit threshold voltage resistor settings r lim (k ) r ds v lim (mv) dcr v lim (mv) 10 0 0 11 5 2.5 12.1 10 5 13.3 15 7.5 14.7 20 10 16.2 25 12.5 17.8 30 15 19.6 35 17.5 21.5 40 20 23.7 45 22.5 26.1 50 25 28.7 55 27.5 31.6 60 30 34.8 65 32.5 38.3 70 35 42.2 75 37.5 46.4 80 40 51.1 85 42.5 56.2 90 45 61.9 95 47.5 68.1 100 50 75 105 52.5 82.5 110 55 90.9 115 57.5 100 120 60
ZL6105 21 fn6906.3 february 8, 2011 loop compensation the ZL6105 operates as a voltage-mode synchronous buck controller with a fixed frequency pwm scheme. although the ZL6105 uses a digital control loop, it operates much like a traditional analog pwm controller. figure 13 is a simplified block diagram of the ZL6105 control loop, which differs from an analog control loop only by the constants in the pwm and compensation blocks. as in the analog controller case, the compensation block compares the output voltage to the desired voltage reference and compensates to keep the loop stable. the resulting integrated error signal is used to drive the pwm logic, converting the error signal to a duty cycle to drive the external mosfets. the ZL6105 has an auto compensation feature that measures the characteristics of the power train and calculates the proper tap coefficients. auto compensati on is configured using the fc0 and fc1 pins as shown in table 16 and table 17. when auto compensation is enabled, the routine can be set to execute one time after ramp or periodically while regulating. note that the auto compensation feature requires a minimum ton_delay as described in ?soft-start delay and ramp times? on page 14. if the device is configured to store auto comp values, the calculated compensation values will be saved in the auto comp store and may be read back through the pid_taps command. if repeat mode is enabled, the first auto comp results after the first ramp will be stored; the values calculated periodically are not stored in the auto comp store. when compensation values are saved in the auto comp store, the device will use those compensation values on subsequent ramps. in repeat mode, the latest auto comp results will always be used during operation. stored auto comp results can only be cleared by disabling auto comp store, which is not permitted while the output is enabled. however, sending the autocomp_control command while enabled in store mode will cause the next results to be stored, overwriting previously stored values. if auto compensation is disabled, the device will use the compensation parameters that are stored in the default_store or user_store. if the pg assert parameter is set to "use pg delay," pg will be asserted according to the power_good_delay command, after which auto comp will begin. when auto comp is enabled, the user must not program a power-good delay that w ill expire before the ramp is finished. if pg assert is set to "aft er auto comp," pg will be asserted immediately after the first auto comp cycle completes (power_good_delay will be ignored). the auto comp gain control scales the auto comp results to allow a trade-off between transi ent response and steady-state duty cycle jitter. a setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. note that if auto comp is enabled, for best results vin must be stable before auto comp begins, as shown in equation 32. the auto compensation function can also be configured via the auto_comp_config command and controlled using the auto_comp_control command over the i 2 c/smbus interface. please refer to application note an2033 for further details. d 1-d v in v out l c dpwm r c compensation r o figure 13. control loop block diagram table 16. fc0 pin-strap settings fc0 pin store values single/repeat pg assert low auto comp disabled open not stored single after auto comp high store in flash single after auto comp 10k ? not stored single after auto comp 11k ? store in flash 12.1k ? not stored repeat ~1 sec 13.3k ? store in flash 14.7k ? not stored single after pg delay 16.2k ? store in flash 17.8k ? not stored repeat ~1 sec 19.6k ? store in flash 21.5k ? not stored single after auto comp 23.7k ? store in flash 26.1k ? not stored repeat ~1 min 28.7k ? store in flash 31.6k ? not stored single after pg delay 34.8k ? store in flash 38.3k ? not stored repeat ~1 min 42.2k ? store in flash vin vin nom -------------------- in% () 100% 1 256 vout ? vin nom ---------------------------- - + -------------------------------------- - (eq. 32)
ZL6105 22 fn6906.3 february 8, 2011 non-linear response (nlr) settings the ZL6105 incorporates a non-li near response (nlr) loop that decreases the response time and the output voltage deviation in the event of a sudden output load current step. the nlr loop incorporates a secondary error signal processing path that bypasses the primary error loop when the output begins to transition outside of the standard regulation limits. this scheme results in a higher equivalent loop bandwidth than what is possible using a traditional linear loop. when a load current step function imposed on the output causes the output voltage to drop below the lower regulation limit, the nlr circuitry will force a positive correction signal that will turn on the upper mosfet and quickly force the output to increase. conversely, a negative load step (i.e. removing a large load current) will cause the nlr circuitry to force a negative correction signal that will turn on the lower mosfet and quickly force the output to decrease. nlr can be configured using re sistor pin-straps as follows: ? cfg0 disables nlr or enables nlr inner thresholds to 1.5%, 2% or 3% (see table 29). ? cfg1 sets nlr inner thresholds timeout and blanking to 1 and 4 or 2 and 8 (see table 26). please refer to a pplication note an2032 for more details regarding nlr settings. efficiency optimized driver dead-time control the ZL6105 utilizes a closed loop algorithm to optimize the dead-time applied between the gate drive signals for the top and bottom fets. in a synchronous buck converter, the mosfet drive circuitry must be designed su ch that the top and bottom mosfets are never in the conducting state at the same time. potentially damaging currents flow in the circuit if both top and bottom mosfets are simultaneously on for periods of time exceeding a few nanoseconds. conversely, long periods of time in which both mosfets are off reduce overall circuit efficiency by allowing current to flow in their parasitic body diodes. it is therefore advantageous to minimize this dead-time to provide optimum circuit efficiency . in the first order model of a buck converter, the duty cycle is determined by equation 33: however, non-idealities exist that cause the real duty cycle to extend beyond the ideal. dead-tim e is one of those non-idealities that can be manipulated to improve efficiency. the ZL6105 has an internal algorithm that constantly adjusts dead-time non-overlap to minimize duty cycle, thus maximizing efficiency. this circuit will null out dead-time differences due to component variation, temperature, and loading effects. this algorithm is independent of a pplication circuit parameters such as mosfet type, gate driver dela ys, rise and fall times and circuit layout. in addition, it does not re quire drive or mosfet voltage or current waveform measurements. adaptive diode emulation most power converters use synchr onous rectification to optimize efficiency over a wide range of input and output conditions. however, at light loads the synchronous mosfet will typically sink current and introduce additi onal energy losses associated with higher peak inductor currents, resulting in reduced efficiency. adaptive diode emulation mode turns off the low-side fet gate drive at low load currents to prevent the inductor current from going negative, reducing the energy losses and increasing overall efficiency. note: the overall bandwidth of the device may be reduced when in diode emulation mode. it is recommended that diode emulation is disabled prior to applying significant load steps. power management functional description input undervoltage lockout the input undervoltage lockout (uvlo) prevents the ZL6105 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. the uvlo threshold (v uvlo ) can be set between 2.85v and 16v using the uvlo pin. the simplest implementation is to connect the uvlo pin as shown in table 18. if the uvlo pin is left unconnected, the uvlo threshold will default to 4.5v. table 17. fc1 pin-strap settings fc1 pin auto comp gain low 100% open 50% high 30% 10k ? 10% 11k ? 20% 12.1k ? 30% 13.3k ? 40% 14.7k ? 50% 16.2k ? 60% 17.8k ? 70% 19.6k ? 80% 21.5k ? 90% 23.7k ? 100% table 18. uvlo threshold pin-strap settings uvlo pin uvlo threshold (v) low 3 open 4.5 high 10.8 in out v v d (eq. 33)
ZL6105 23 fn6906.3 february 8, 2011 if the desired uvlo threshold is no t one of the listed choices, the user can configure a threshold between 2.85v and 16v by connecting a resistor between the uvlo pin and sgnd by selecting the appropriate resistor from table 19. the uvlo voltage can also be set to any value between 2.85v and 16v via the i 2 c/smbus interface. once an input undervoltage faul t condition occurs, the device can respond in a number of ways as follows: 1. continue operating without interruption. 2. continue operating for a given delay period, followed by shutdown if the fault still exists. the device will remain in shutdown until instructed to restart. 3. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. the default response from a uvlo fault is an immediate shutdown of the device. the devi ce will continuously check for the presence of the fault condition. if the fault condition is no longer present, the ZL6105 will be re-enabled. please refer to appl ication note an2033 for details on how to configure the uvlo threshold or to select specific uvlo fault response options via the i 2 c/smbus interface. output overvoltage protection the ZL6105 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. a hardware comparator is used to compare the actual output voltage (seen at the vsen pin) to a threshold set to 15% higher than the target output voltage (t he default setting). if the vsen voltage exceeds this threshold, the pg pin will de-assert and the device can then respond in a number of ways as follows: 1. initiate an immediate shutdo wn until the fault has been cleared. the user can select a specific number of retry attempts. 2. turn off the high-side mosfet and turn on the low-side mosfet. the low-side mosfet remains on until the device attempts a restart. the default response from an over voltage fault is to immediately shut down. the device will contin uously check for the presence of the fault condition, and when the fault condition no longer exists the device will be re-enabled. for continuous overvoltage protec tion when operating from an external clock, the only allowed response is an immediate shutdown. please refer to application no te an2033 for details on how to select specific overvoltage fault response options via i 2 c/smbus. output pre-bias protection an output pre-bias condition exists when an externally applied voltage is present on a power supply?s output before the power supply?s control ic is enabled. certain applications require that the converter not be allowed to sink current during start up if a pre-bias condition exists at th e output. the ZL6105 provides pre-bias protection by sampling the output voltage prior to initiating an output ramp. if a pre-bias voltage lower than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled. the output voltage is then ramped to the final regulation value at the ramp rate set by the ss pin. the actual time the output will take to ramp from the pre-bias voltage to the target voltage will vary depending on the pre-bias voltage but the total time elapse d from when the delay period expires and when the output reaches its target value will match the pre-configured ramp time. see figure 14. if a pre-bias voltage higher than the target voltage exists after the pre-configured delay period has expired, the target voltage is set to match the existing pre-bias voltage and both drivers are enabled with a pwm duty cycle that would ideally create the pre- bias voltage. once the pre-configured soft-start ramp period has expired, the pg pin will be asserted (assuming the pre-bias voltage is not higher than the overvoltage limit) . the pwm will then adjust its duty cycle to match the original target voltage and the output will ramp down to the pre-configured output voltage. if a pre-bias voltage higher than the overvoltage limit exists, the device will not initiate a turn-o n sequence and will declare an overvoltage fault condition to exist. in this case, the device will respond based on the output overvoltage fault response method that has been selected. see ?output overvoltage protection? on page 23 for response options due to an overvoltage condition. table 19. uvlo threshold resistor settings r uvlo (k ) uvlo (v) r uvlo (k ) uvlo (v) 17.8 2.85 46.4 7.42 19.6 3.14 51.1 8.18 21.5 3.44 56.2 8.99 23.7 3.79 61.9 9.9 26.1 4.18 68.1 10.9 28.7 4.59 75 12 31.6 5.06 82.5 13.2 34.8 5.57 90.9 14.54 38.3 6.13 100 16 42.2 6.75
ZL6105 24 fn6906.3 february 8, 2011 output overcurrent protection the ZL6105 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. once the current lim it threshold has been selected (see ?current limit threshold selection? on page 19), the user may determine the desired course of action in response to the fault condition. the following overcurrent protection response options are available: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. the default response from an ov ercurrent fault is an immediate shutdown of the device. the devi ce will continuously check for the presence of the fault condition, and if the fault condition no longer exists the device will be re-enabled. please refer to appl ication note an2033 for details on how to select specific overcurrent fault response options via i 2 c/smbus. thermal overload protection the ZL6105 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. the default temperature limit is set to +125c in the factory, but the user may set the limit to a different value if desired. see application note an2033 for details. note that setting a higher thermal limit via the i 2 c/smbus interface may result in permanent damage to the device. once the device has been disabled due to an internal temperature fault, the user may select one of several fault response options as follows: 1. initiate a shutdown and attempt to restart an infinite number of times with a preset delay period between attempts. 2. initiate a shutdown and attempt to restart a preset number of times with a preset delay period between attempts. 3. continue operating for a given delay period, followed by shutdown if the fault still exists. 4. continue operating through th e fault (this could result in permanent damage to the power supply). 5. initiate an immediate shutdown. if the user has configured the devi ce to restart, the device will wait the preset delay period (if configured to do so) and will then check the device temperature. if the temperature has dropped below a threshold that is appr oximately +15c lower than the selected temperature fault limit, the device will attempt to re- start. if the temperature still ex ceeds the fault li mit the device will wait the preset delay period and retry again. the default response from a temp erature fault is an immediate shutdown of the device. the device will continuously check for the fault condition, and once the fault has cleared the ZL6105 will be re-enabled. please refer to application note an2033 for details on how to select specific temperature faul t response options via i 2 c/smbus. voltage tracking numerous high performance sy stems place stringent demands on the order in which the power supply voltages are turned on. this is particularly true when powering fpgas, asics, and other advanced processor devices that require multiple supply voltages to power a single die. in most ca ses, the i/o interface operates at a higher voltage than the core and therefore the core supply voltage must not exceed the i/o supply voltage according to the manufacturers' specifications. voltage tracking protects these sensitive ics by limiting the differential voltage between multiple power supplies during the power-up and power down sequence. the ZL6105 integrates a lossless tracking scheme that allo ws its output to track a voltage that is applied to the vtrk pin with no external components required. the vtrk pin is an an alog input that, when tracking mode is enabled, configures the voltage applied to the vtrk pin to act as a reference for the device?s output regulation. the ZL6105 offers two modes of tracking as follows: 1. coincident . this mode configures the ZL6105 to ramp its output voltage at the same rate as the voltage applied to the vtrk pin. figure 14. output responses to pre-bias voltages
ZL6105 25 fn6906.3 february 8, 2011 2. ratiometric . this mode configures the ZL6105 to ramp its output voltage at a rate that is a percentage of the voltage applied to the vtrk pin. the default setting is 50%, but an external resistor string may be used to configure a different tracking ratio. figure 15 illustrates the typical connection and the two tracking modes. the master ZL6105 device in a tracking group is defined as the device that has the highest target output voltage within the group. this master device will control the ramp rate of all tracking devices and is not configured for tracking mode. a delay of at least 10ms must be configured into the master device using the ss pin, and the user may also configure a specific ramp rate using the ss pin. any device that is configured for tracking mode will ignore its soft-start delay an d ramp time settings (ss pin) and its output will take on the turn-o n/turn-off characteristics of the reference voltage present at the vtrk pin. all of the enable pins in the tracking group must be connected together and driven by a single logic source. tracking is configured via the i 2 c/smbus interface by using the track_config pmbus command. please refer to application note an 2033 for more information on configuring tracking mode using pmbus. when a current sharing rail is tracking, the on-delay time of the voltage being tracked must not exceed the on-delay of the tracking rail by 5ms. voltage margining the ZL6105 offers a simple means to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. the mgn command is set by driving the mgn pin or through the i 2 c/smbus interface. the mgn pin is a tri-level input that is continuous ly monitored and can be driven directly by a processor i/o pin or other logic-level output. the ZL6105?s output will be forc ed higher than its nominal set point when the mgn command is set high, and the output will be forced lower than its nominal set point when the mgn command is set low. default margin limits of v nom 5% are pre-loaded in the factory, but the margin limits can be modified through the i 2 c/smbus interface to as high as v nom + 10% or as low as 0v, where v nom is the nominal output voltage set point determined by the v0 and v1 pins. the ZL6105-01 allows 150% margin limits. the margin limits and the mg n command can both be set individually through the i 2 c/smbus interface. additionally, the transition rate between the nomi nal output voltage and either margin limit can be configured through the i 2 c interface. please refer to application note an2033 for detailed instructions on modifying the margining configurations. i 2 c/smbus communications the ZL6105 provides an i 2 c/smbus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. the ZL6105 can be used with any standard 2-wire i 2 c host device. in addition, the device is compatible with smbus version 2.0 and includes an salrt line to help mitigate bandwidth limitations related to continuous fault monitoring. pull-up resistors are required on the i 2 c/smbus as specified in the smbus 2.0 specification. the ZL6105 accepts most standard pmbus commands. when controlling the device with pmbus commands, it is recommended that the enable pin is tied to sgnd. i 2 c/smbus device address selection when communicating with multiple smbus devices using the i 2 c/smbus interface, each device must have its own unique v out v out time coincident ratiometric v trk v in v out q1 q2 l1 c1 gh gl sw zl vtrk v trk v out v out time v trk figure 15. tracking modes table 20. tracking resistor settings r ss (k ) track ratio (%) upper track limit ramp-up/down behavior 90.9 100 limited by target output does not decrease before pg 100 output always follows vtrk 110 limited by vtrk output does not decrease before pg 121 output always follows vtrk 133 50 limited by target output does not decrease before pg 147 output always follows vtrk 162 limited by vtrk output does not decrease before pg 178 output always follows vtrk
ZL6105 26 fn6906.3 february 8, 2011 address so the host can distinguish between the devices. the device address can be set according to the pin-strap options listed in table 21. address values are right-justified. if additional device addresses are required, a resistor can be connected to the sa0 pin according to table 22 to provide up to 25 unique device addresses. in this case, the sa1 pin should be tied to sgnd. if more than 25 unique device addresses are required or if other smbus address values are desired, both the sa0 and sa1 pins can be configured with a resistor to sgnd according to equation 34 and table 23. note that the smbus address 0x4b is reserved for device test and cannot be used in the system. using this method, the user can th eoretically configure up to 625 unique smbus addresses, howe ver the smbus is inherently limited to 128 devices so attemp ting to configure an address higher than 128 (0x80) will cause the device address to repeat (i.e., attempting to configure a device address of 129 (0x81) would result in a device address of 1). therefore, the user should use index values 0 to 4 on the sa 1 pin and the full range of index values on the sa0 pin, which will provide 125 device address combinations. to determine the sa0 and sa1 resistor values given an smbus address (in decimal), follow the indicated steps to calculate an index value and then use table 23 to select the resistor that corresponds to the calculated index value as follows: 1. calculate sa1 index: 2. round the result down to the nearest whole number. 3. select the value of r1 from table 23 using the sa1 index rounded value from step 2. 4. calculate sa0 index: 5. select the value of r0 from table 23 using the sa0 index value from step 4. digital-dc bus the digital-dc communications (ddc) bus is used to communicate between zilker labs digital-dc devices. this dedicated bus provides the communication channel between devices for features such as sequencing, fault spreading, and current sharing. the ddc pin on all digital-dc devices in an application should be connected together. a pull-up resistor is required on the ddc bus in order to guarantee the rise time as follows: where r pu is the ddc bus pull-up resistance and c load is the bus loading. the pull-up resistor may be tied to vr or to an external 3.3v or 5v supply as long as this voltage is present prior to or table 21. smbus address pin-strap selection sa0 low open high sa1 low 0x20 0x21 0x22 open 0x23 0x24 0x25 high 0x26 0x27 reserved table 22. smbus address resistor selection r sa0 (k ) smbus address r sa0 (k ) smbus address 10 0x00 34.8 0x0d 11 0x01 38.3 0x0e 12.1 0x02 42.2 0x0f 13.3 0x03 46.4 0x10 14.7 0x04 51.1 0x11 16.2 0x05 56.2 0x12 17.8 0x06 61.9 0x13 19.6 0x07 68.1 0x14 21.5 0x08 75 0x15 23.7 0x09 82.5 0x16 26.1 0x0a 90.9 0x17 28.7 0x0b 100 0x18 31.6 0x0c table 23. smbus address index values r sa (k ) sa0 or sa1 index r sa (k ) sa0 or sa1 index 10 0 34.8 13 11 1 38.3 14 12.1 2 42.2 15 smbus address = 25 x (sa1 index) + (sa0 index) (eq. 34) (in decimal) 13.3 3 46.4 16 14.7 4 51.1 17 16.2 5 56.2 18 17.8 6 61.9 19 19.6 7 68.1 20 21.5 8 75 21 23.7 9 82.5 22 26.1 10 90.9 23 28.7 11 100 24 31.6 12 table 23. smbus address index values r sa (k ) sa0 or sa1 index r sa (k ) sa0 or sa1 index sa1 index = address (in decimal) 25 (eq. 35) sa0 index = address - (25 x sal index) (eq. 36) risetime r pu ? c load 1 s = (eq. 37)
ZL6105 27 fn6906.3 february 8, 2011 during device power-up. as rules of thumb, each device connected to the ddc bus presents ~10pf of capacitive loading, and each inch of fr4 pcb trace introduces ~2pf. the ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. in power module applications, the user should consider whether to place the pull-up resistor on the module or on the pcb of the end application. the minimum pull- up resistance should be limited to a value that enables any device to assert the bus to a vo ltage that will en sure a logic 0 (typically 0.8v at the device mo nitoring point) given the pull-up voltage (5v if tied to vr) and th e pull-down current capability of the ZL6105 (nominally 4ma). phase spreading when multiple point of load converters share a common dc input supply, it is desirable to adjust the clock phase offset of each device such that not all devices start to switch simultaneously. setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the i rms 2 are reduced dramatically. in order to enable phase spreading, all converters must be synchronized to the same switchin g clock. the cfg1 pin is used to set the configuration of the sync pin for each device as described in ?switching frequency and pll? on page 15. the phase offset of each single-phase device may be set to any value between 0 and 337.5 in 22.5 increments using the cfg2 pin as shown in tables 24 and 25. table 24. phase offset pin-strap settings r cfg2 phase offset () current sense low 90 dcr open 0 high 180 table 25. phase offset resistor settings r cfg2 (k ) phase offset () current sense 10 22.5 dcr 11 45 12.1 67.5 13.3 90 14.7 112.5 16.2 135 17.8 157.5 19.6 180 21.5 202.5 23.7 225 26.1 247.5 28.7 270 31.6 292.5 34.8 315 38.3 337.5 42.2 22.5 rds 46.4 45 51.1 67.5 56.2 90 61.9 112.5 68.1 135 75 157.5 82.5 180 90.9 202.5 100 225 110 247.5 121 270 133 292.5 147 315 162 337.5
ZL6105 28 fn6906.3 february 8, 2011 the phase offset of (multi-pha se) current sharing devices is automatically set to a value between 0 and 337.5 in 22.5 increments as described in ?phase spreading? on page 27. the phase offset of each device may also be set to any value between 0 and 360 in 22.5 increments via the i 2 c/smbus interface. refer to application note an2033 for further details. output sequencing a group of digital-dc devices may be configured to power up in a predetermined sequence. this feature is especially useful when powering advanced processors, fpgas, and asics that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. multi-device sequencing can be achieved by configuring each device through the i 2 c/smbus interface or by using zilker labs patented autonomous sequencing mode. autonomous sequencing mode co nfigures sequencing by using events transmitted between devices over the ddc bus. this mode is not available on current sharing rails. the sequencing order is determined using each device?s smbus address. using autonomous sequencing mode (configured using the cfg1 pin), the devices must be assigned sequential smbus addresses with no missing addresse s in the chain. this mode will also constrain each device to have a phase offset according to its smbus address as desc ribed in ?phase spreading? on page 27. the sequencing group will turn on in order starting with the device with the lowest smbus ad dress and will continue through to turn on each device in the address chain until all devices connected have been turned on. when turning off, the device with the highest smbus address will turn off first followed in reverse order by the other devices in the group. sequencing is configured by conne cting a resistor from the cfg1 pin to ground as described in table 26. the cfg1 pin is also used to set the configuration of the sync pin as well as to determine the sequencing method and order. please refer to ?switching frequency and pll? on page 15 fo r more details on the operating parameters of the sync pin. multiple device sequencing may al so be achieved by issuing pmbus commands to assign the preceding device in the sequencing chain as well as the device that will follow in the sequencing chain. this method places fewer restrictions on smbu s address (no need of sequential address) and also allows the user to assign any phase offset to any device irrespective of its smbus device address. the enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. enable must be driven lo w to initiate a sequenced turnoff of the group. refer to application note an2033 for details on sequencing via the i 2 c/smbus interface. fault spreading digital-dc devices can be config ured to broadcast a fault event over the ddc bus to the other devices in the group. when a non- destructive fault occurs and the devi ce is configured to shut down on a fault, the device will shut down and broadcast the fault event over the ddc bus. the other devices on the ddc bus will shut down together or in sequencing order if configured to do so, and will attempt to re-start in th eir prescribed order if configured to do so. temperature monitoring using the xtemp pin the ZL6105 supports measurement of an external device temperature using either a thermal diode integrated in a processor, fpga or asic, or us ing a discrete diode-connected 2n3904 npn transistor. figure 16 illustrates the typical connections required. active current sharing paralleling multiple ZL6105 devices can be used to increase the output current capability of a sing le power rail. by connecting the ddc pins of each device together and configuring the devices as a current sharing rail, the units will share the current equally within a few percent. figure 17 illustrates a typical connection for three devices. the ZL6105 uses a low-bandwidth, first-order digital current sharing technique to balance the unequal device output loading by aligning the load lines of member devices to a reference device. droop resistance is used to add ar tificial resistance in the output voltage path to control the slope of the load line curve, calibrating out the physical parasitic mismatches due to power train components and pcb layout. a minimum droop resistance of 0.5m ? is recommended. zl sgnd xtemp discrete npn 2n3904 zl sgnd xtemp embedded thermal diode p fpga dsp asic 100 pf 100 pf figure 16. external temperature monitoring
ZL6105 29 fn6906.3 february 8, 2011 table 26. sequencing pin-st rap and resistor settings r cfg1 sync pin config sequencing configuration nlr timeout and blanking low input sequencing is disabled. 1 and 4 open auto detect high output 10k input sequencing is disabled. 1 and 4 11k auto detect 12.1k output 14.7k input the ZL6105 is configured as the first device in a nested sequencing group. turn on order is based on the device smbus address. 16.2k auto detect 17.8k output 21.5 k input the ZL6105 is configured as a last device in a nested sequencing group. turn on order is based on the device smbus address. 23.7k auto detect 26.1k output 31.6k input the ZL6105 is configured as th e middle device in a nested sequencing group. turn on order is based on the device smbus address. 34.8k auto detect 38.3k output 46.4 k input sequencing is disabled. 2 and 8 51.1 k auto detect 56.2 k output 68.1 k input the ZL6105 is configured as the first device in a nested sequencing group. turn on order is based on the device smbus address. 75 k auto detect 82.5 k output 100 k input the ZL6105 is configured as a last device in a nested sequencing group. turn on order is based on the device smbus address. 110 k auto detect 121 k output 147 k input the ZL6105 is configured as th e middle device in a nested sequencing group. turn on order is based on the device smbus address. 162 k auto detect 178 k output zl v out zl zl v in c out c in c out c in c out c in ddc ddc ddc 3.3v - 5v figure 17. current sharing group -r -r v reference v member i member i reference i out v out figure 18. active current sharing
ZL6105 30 fn6906.3 february 8, 2011 upon system start-up, the devi ce with the lowest member position as selected in ishare_config is defined as the reference device. the remaining devices are members. the reference device broadcasts its current over the ddc bus. the members use the reference current information to trim their voltages (v member ) to balance the current loading of each device in the system. figure 18 shows that, for load lines with identical slopes, the member voltage is increased towards the reference voltage which closes the gap between the inductor currents. the relation between reference and member current and voltage is given by equation 38: where r is the value of the droop resistance. the ishare_config command is used to configure the device for active current sharing. the default setting is a stand-alone non-current sharing device. a current sharing rail can be part of a system sequencing group. for fault configuration, the curren t share rail is configured in a quasi-redundant mode. in this mode, when a member device fails, the remaining members will continue to operate and attempt to maintain regulation. of the remaining devices, the device with the lowest member position will become the reference. if fault spreading is enabled, the current share rail failure is not broadcast until the entire current share rail fails. when auto compensation is enabled, only two (2) devices can be configured for current sharing. with auto compensation disabled, up to eight (8) devices can be configured in a given current sharing rail. table 27. current share position settings r cfg2 (k ) current share position current sense 10 0 dcr 11 1 12.1 2 13.3 3 14.7 4 16.2 5 17.8 6 19.6 7 42.2 0 rds 46.4 1 51.1 2 56.2 3 61.9 4 68.1 5 75 6 82.5 7 () member reference out member i i r v v ? + = (eq. 38) table 28. current share pin-strap settings cfg0 pin nlr current share # of members current sharing low 1.5% 0 disabled open disabled high 2% table 29. current share resistor settings r cfg0 (k )nlr current share # of members current sharing 10 disabled 2 enabled 11 3 12.1 4 13.3 5 14.7 6 16.2 7 17.8 8 19.6 3% 0 disabled 21.5 2 enabled 23.7 3 26.1 4 28.7 5 31.6 6 34.8 7 38.3 8 42.2 2% 0 disabled 46.4 2 enabled 51.1 3 56.2 4 61.9 5 68.1 6 75 7 82.5 8 90.9 1.5% 0 disabled 100 2 enabled 110 3 121 4 133 5 147 6 162 7 178 8
ZL6105 31 fn6906.3 february 8, 2011 the phase offset of a current sharing group is automatically set to a value between 0 and 337.5 in 22.5 increments as follows: the phase of the individual me mbers in a group are spread evenly from the phase offset of the group. please refer to application note an2034 for additional details on current sharing. phase adding/dropping the ZL6105 allows multiple power converters to be connected in parallel to supply higher load currents than can be addressed using a single-phase design. in doing so, the power converter is optimized at a load current range that requires all phases to be operational. during periods of light loading, it may be beneficial to disable one or more phases in order to eliminate the current drain and switching losses asso ciated with those phases, resulting in higher efficiency. the ZL6105 offers the ability to add and drop phases using a the phase enable pin or a pmbus command in response to an observed load current change. all phases in a current share rail are considered active prior to the current sharing rail ramp to power-good. phases can be dropped after power-good is reached. the phase enable pin can be used to drop and add phases: ? set ph_en = 0 to drop a phase ? set ph_en = 1 to add a phase the time to detect a change of state of the phase enable pin is between 0ms and 3ms (max). any member of the current sharing rail can be dropped. any change to the number of members of a current sharing rail will precipitate autonomous phase dist ribution within the rail where all active phases realign their phase position based on their order within the number of active members. if the members of a current sharing rail are forced to shut down due to an observed fault, all members of the rail will attempt to re-start simultaneously after the fault has cleared. for single phase operation, that is, not current sharing, the ph_en pin is ignored and can be left open. monitoring via i 2 c/smbus a system controller can monitor a wide variety of different ZL6105 system parameters through the i 2 c/smbus interface. the device can monitor for fault conditions by monitoring the salrt pin, which will be pulled low when any number of pre- configured fault conditions occur. the device can also be monitored continuously for any number of power conversion parameters including but not limited to the following: ? input voltage/output voltage ? output current ? internal and external temperature ? switching frequency ? duty cycle the pmbus host should resp ond to salrt as follows: 1. zl device pulls salrt low. 2. pmbus host detects that salrt is now low, performs transmission with alert respon se address to find which zl device is pulling salrt low. 3. pmbus host talks to the zl device that has pulled salrt low. the actions that the host performs are up to the system designer. if multiple devices are faulting, salrt will still be low after doing the above steps and will require transmission with the alert response address repeatedly until all faults are cleared. please refer to application no te an2033 for details on how to monitor specific parameters via the i 2 c/smbus interface. snapshot parameter capture the ZL6105 offers a special feat ure that enables the user to capture parametric data during normal operation or following a fault. the snapshot functionality is enabled by setting bit 1 of misc_config to 1. see an2033 for details on using th e snapshot in addition to the parameters supported. the snapshot feature enables the user to read status and parameters via a block read transfer through the smbus. this can be done during normal operation, although it should be noted that reading the 22 bytes will occupy the smbus for some time. the snapshot_control command enables the user to store the snapshot parameters to fl ash memory in response to a pending fault as well as to read the stored data from flash memory after a fault has occurred. table 30 describes the usage of this command. automatic writes to flash memory following a fault are triggered when any faul t threshold level is exceeded, provided that the specific faul t?s response is to shut down (writing to flash memory is not allowed if the device is configured to re-try following the specific fault condition). it should also be noted that the device?s v dd voltage must be maintained during the time when the device is writing the data to flash memory; a process that requires between 700s to 1400s depending on whether the data is set up for a block write. undesirable results may be observed if the device?s v dd supply drops below 3.0v during this process. (eq. 39) phase offset = (smbus address[4:0] ? current share position) * 22.5 table 30. snapshot_control command data value description 1 copies current snapshot values from flash memory to ram for immediate access using snapshot command. 2 writes current snapshot valu es to flash memory. only available when device is disabled.
ZL6105 32 fn6906.3 february 8, 2011 in the event that the device experiences a fault and power is lost, the user can extract the last snapshot parameters stored during the fault by writing a 1 to snapshot_control (transfers data from flash memory to ram) and then issuing a snapshot command (reads data from ram via smbus). non-volatile memory and device security features the ZL6105 has internal non-volatile memory where user configurations are stored. integr ated security measures ensure that the user can only restore the device to a level that has been made available to them. refer to ?start-up procedure? on page 13 for details on how the device loads stored values from internal memory during start-up. during the initialization process, the ZL6105 checks for stored values contained in its internal non-volatile memory. the ZL6105 offers two internal memory stor age units that ar e accessible by the user as follows: 1. default store: a power supply module manufacturer may want to protect the module from damage by preventing the user from being able to modify certain values that are related to the physical construction of the module. in this case, the module manufacturer would use the default store and would allow the user to restore the de vice to its default setting but would restrict the user from restoring the device to the factory settings. 2. user store: the manufacturer of a piece of equipment may want to provide the ability to modify certain power supply settings while still protecting the equipment from modifying values that can lead to a system level fault. the equipment manufacturer would use the user store to achieve this goal. please refer to application note an2033 for details on how to set specific security measures via the i 2 c/smbus interface.
ZL6105 33 fn6906.3 february 8, 2011 revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 12/15/10 fn6906.3 in ?voltage margining? on page 25, in the 2nd paragraph, changed the last sentence from "a safety feature preven ts the user from configuring the output voltage to exceed vnom + 10% under any conditions." to "the ZL6105-0 1 allows 150% margin limits." added following parts to ?ordering information? on page 5: ZL6105alaf-01 ZL6105alaft-01 ZL6105alaftk-01 updated note in min, max column of spec table from "param eters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by ch aracterization and are not produc tion tested." to "compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." removed note "limits established by characterization and are not production tested." and all references to it. 12/8/10 fn6906.2 added following statement to disclaimer on page 34: ?this product is subject to a li cense from power one, inc. r elated to digital power technology as set forth in u.s. patent no. 7,000,125 an d other related patents owned by power one, inc. these license rights do not extend to stand-alone pol regulators unless a royalty is paid to power one, inc.? 9/20/10 fn6906.1 -added a second sentence ("a minimum droop re sistance of 0.5m ? is recommended.") to ?active current sharing? on page 28 -on page 21, in equation 32, changed " " to " ". -added ?limits established by characterization and are not producti on tested.? to ?soft-start delay duration range? on page 8, ?soft-start ramp duration range? on page 8 and ?vtrk regulation accuracy? on page 8. -removed pg and salrt from conditions column of ?logic input leakage current? on page 8. 9/14/10 -added table 8 ?minimum ton delay vs operating mode? -added the following paragraph to page 14: "the ZL6105 has a minimum ton_delay requiremen t ... see application note an2033 for details." -changed low delay time from "2" to "5" in table 6 on page 14 -removed first three rows (10, 11, and 12.1 rows) from table 7 on page 14 -rewrote paragraph directly above figure 13 on page 21 (?when auto compensation is enabled ... as described in ?soft-start delay and ramp times? on page 14") -changed min ?soft-start delay duration range? on page 8 from 2 to 5 and 0.002 to 0.005 -reworded note 15 on page 9 -changed step 5 description in table 5 on page 14 -replaced step 5 time duration entry in table 5 on page 14 with a dash (?-?) -rewrote paragraph on page 13 (?once this process is completed...to ramp its output?) -replaced table 16 ?fc0 pin-strap settings? on page 21 -replaced table 17 ?fc1 pin-strap settings? on page 22 -rewrote the last three paragraphs of ?loop compensation? on page 21 -added third paragraph to ?power-good? on page 15 (?if auto comp is enabled, the pg timing is further controlled by the pg assert parameter as described ?loop compensation? on page 21.?) -added sentence to note 17 on page 9 ("refer to ?soft-start delay and ramp times? on page 14 for further restrictions on pg delay.") -in?soft-start delay duration accuracy? on page 8, in the conditions, changed both references to note 16 to be note 15. removed note 16. -rewrote first paragraph of ?configuration b: sync input? on page 15 -rewrote first three paragraphs of ?configuration c: sync auto detect? on page 15 -added sentence just before table 23 on page 26 (?note that the smbus address 0x4b is reserved for device test and cannot be used in the system.?) 8/5/10 on page 1, 1st sentence, changed "the ZL6105 is a digital dc/dc controller ?" to "the ZL6105 is a digital power controller ?" on page 1, 2nd paragraph, end of 1st sentence, changed from "? 3.3v to a supply operating from a 12v input." to "? 3.3v to a multiphase current sharing supply operating from a 12v input." on page 2, figure 3, added arrow head to line going into pin 34 (ph_en) on page 2, note 3, 3rd sentence, corrected the ohm symbol after 10k,which was missing. on page 5, note 1, corrected "pindependents" to "pin dependents" on page 8, ?vtrk tracking ramp accuracy?, in the conditions column, added "no prebias" on page 9, typ entry in table for ?current limit protection delay? (condition factory default): changed from 5 to 10 on page 9, note 15 at bottom of table, 3rd sentence, corrected from "current share reference must be 10ms ?", to "current share reference delay must be 10ms ?" on page 13, corrected the font size for title ?smbus mode? (to be the same font as the title ?single resistor output voltage setting mode?) on page 14, 1st column, 2nd paragraph, ?soft-start delay and ra mp times?, removed last two sentences, "precise ramp delay timing ? an2033 for details."
ZL6105 34 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. this product is subject to a license from po wer one, inc. related to digital power technology as set forth in u.s. patent no. 7 ,000,125 and other related patents owned by power one, inc. these license rights do not extend to stand-alone pol regulators unless a royalty is paid to power one , inc. for information regarding intersil corporation and its products, see www.intersil.com fn6906.3 february 8, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ZL6105 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php 8/4/10 fn6906.1 (cont?d) on page 30, 2nd column, 3rd paragraph, changed from "up to ei ght (8) devices can be configured in a given current sharing rail." to "when auto compensation is enabled, only two (2 ) devices can be configured for current sharing. with auto compensation disabled, up to eight (8) devices ca n be configured in a given current sharing rail." 5/17/10 fn6906.0 initial release revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. (continued) date revision change
ZL6105 35 fn6906.3 february 8, 2011 package outline drawing l36.6x6a 36 lead quad flat no-lead plastic package rev 1, 9/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view ( 4. 10 ) ( 5. 60 typ ) (36x 0.25 ) ( 36x 0.80 ) ( 36 x 0 . 50 ) 0 . 00 min. 0 . 05 max. 0 . 2 ref c max 0.90 5 0.10 c 0.08 c c 6.00 (4x) 0.15 6 pin 1 index area 6.00 b a 4 .10 0.10 36x 0.60 0.10 36x 0.25 c 0.10 m a b 4 19 18 9 10 pin #1 27 28 36x 1 36 0.50 6 4.0 4x index area compliant to jedec mo-220vjjd. 7.

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